This is just a clone of:
https://asics.chuckbenz.com/#My_open_source_8b10b_encoderdecoder
I will copy only relevant part of that page, just in case the page disappears:
My open source 8b10b encoder/decoder
I was not comfortable using the opencores.org 8b10b encoder/decoder because it's licensing terms were unclear to me - particularly whether LGPL when applied to hardware might still be in some way viral, and also because when reusing verilog code, it's inevitable that you need to change it slightly - at least the module name is commonly changed, and the terms seemed to prevent even that. I'm willing to share this implementation very freely. Here you will find an 8b10b encoder, a 8b10b decoder, and a testbed to prove them, all in verilog. Also, a table used by the testbench for the codes - this is raw 1's and 0's taken from a standard. So, the encoder/decoder files are:
encode.v
decode.v
validate_8b10b.v
8b10b_a.mem
8b/10b is of course now used for Fiberchannel, Gigabit Ethernet, 10Gigabit Ethernet, Infiniband, and PCI-Express.