@@ -453,6 +453,14 @@ Form::DataType InstructForm::is_ideal_store() const {
453453 return _matrule->is_ideal_store ();
454454}
455455
456+ // Return 'true' if this instruction matches an ideal vector node
457+ bool InstructForm::is_vector () const {
458+ if ( _matrule == nullptr ) return false ;
459+
460+ return _matrule->is_vector ();
461+ }
462+
463+
456464// Return the input register that must match the output register
457465// If this is not required, return 0
458466uint InstructForm::two_address (FormDict &globals) {
@@ -759,6 +767,51 @@ int InstructForm::memory_operand(FormDict &globals) const {
759767 return NO_MEMORY_OPERAND ;
760768}
761769
770+ // This instruction captures the machine-independent bottom_type
771+ // Expected use is for pointer vs oop determination for LoadP
772+ bool InstructForm::captures_bottom_type (FormDict &globals) const {
773+ if (_matrule && _matrule->_rChild &&
774+ (!strcmp (_matrule->_rChild ->_opType ," CastPP" ) || // new result type
775+ !strcmp (_matrule->_rChild ->_opType ," CastDD" ) ||
776+ !strcmp (_matrule->_rChild ->_opType ," CastFF" ) ||
777+ !strcmp (_matrule->_rChild ->_opType ," CastII" ) ||
778+ !strcmp (_matrule->_rChild ->_opType ," CastLL" ) ||
779+ !strcmp (_matrule->_rChild ->_opType ," CastVV" ) ||
780+ !strcmp (_matrule->_rChild ->_opType ," CastX2P" ) || // new result type
781+ !strcmp (_matrule->_rChild ->_opType ," DecodeN" ) ||
782+ !strcmp (_matrule->_rChild ->_opType ," EncodeP" ) ||
783+ !strcmp (_matrule->_rChild ->_opType ," DecodeNKlass" ) ||
784+ !strcmp (_matrule->_rChild ->_opType ," EncodePKlass" ) ||
785+ !strcmp (_matrule->_rChild ->_opType ," LoadN" ) ||
786+ !strcmp (_matrule->_rChild ->_opType ," LoadNKlass" ) ||
787+ !strcmp (_matrule->_rChild ->_opType ," CreateEx" ) || // type of exception
788+ !strcmp (_matrule->_rChild ->_opType ," CheckCastPP" ) ||
789+ !strcmp (_matrule->_rChild ->_opType ," GetAndSetP" ) ||
790+ !strcmp (_matrule->_rChild ->_opType ," GetAndSetN" ) ||
791+ !strcmp (_matrule->_rChild ->_opType ," RotateLeft" ) ||
792+ !strcmp (_matrule->_rChild ->_opType ," RotateRight" ) ||
793+ #if INCLUDE_SHENANDOAHGC
794+ !strcmp (_matrule->_rChild ->_opType ," ShenandoahCompareAndExchangeP" ) ||
795+ !strcmp (_matrule->_rChild ->_opType ," ShenandoahCompareAndExchangeN" ) ||
796+ #endif
797+ !strcmp (_matrule->_rChild ->_opType ," StrInflatedCopy" ) ||
798+ !strcmp (_matrule->_rChild ->_opType ," VectorCmpMasked" )||
799+ !strcmp (_matrule->_rChild ->_opType ," VectorMaskGen" )||
800+ !strcmp (_matrule->_rChild ->_opType ," VerifyVectorAlignment" )||
801+ !strcmp (_matrule->_rChild ->_opType ," CompareAndExchangeP" ) ||
802+ !strcmp (_matrule->_rChild ->_opType ," CompareAndExchangeN" ))) return true ;
803+ else if ( is_ideal_load () == Form::idealP ) return true ;
804+ else if ( is_ideal_store () != Form::none ) return true ;
805+
806+ if (needs_base_oop_edge (globals)) return true ;
807+
808+ if (is_vector ()) return true ;
809+ if (is_mach_constant ()) return true ;
810+
811+ return false ;
812+ }
813+
814+
762815// Access instr_cost attribute or return null.
763816const char * InstructForm::cost () {
764817 for (Attribute* cur = _attribs; cur != nullptr ; cur = (Attribute*)cur->_next ) {
@@ -1128,6 +1181,9 @@ const char *InstructForm::mach_base_class(FormDict &globals) const {
11281181 }
11291182 else if (is_mach_constant ()) {
11301183 return " MachConstantNode" ;
1184+ }
1185+ else if (captures_bottom_type (globals)) {
1186+ return " MachTypeNode" ;
11311187 } else {
11321188 return " MachNode" ;
11331189 }
@@ -4281,6 +4337,58 @@ Form::DataType MatchRule::is_ideal_load() const {
42814337 return ideal_load;
42824338}
42834339
4340+ bool MatchRule::is_vector () const {
4341+ static const char *vector_list[] = {
4342+ " AddVB" ," AddVS" ," AddVI" ," AddVL" ," AddVHF" ," AddVF" ," AddVD" ,
4343+ " SubVB" ," SubVS" ," SubVI" ," SubVL" ," SubVHF" ," SubVF" ," SubVD" ,
4344+ " MulVB" ," MulVS" ," MulVI" ," MulVL" ," MulVHF" ," MulVF" ," MulVD" ,
4345+ " DivVHF" ," DivVF" ," DivVD" ,
4346+ " AbsVB" ," AbsVS" ," AbsVI" ," AbsVL" ," AbsVF" ," AbsVD" ,
4347+ " NegVF" ," NegVD" ," NegVI" ," NegVL" ,
4348+ " SqrtVD" ," SqrtVF" ," SqrtVHF" ,
4349+ " AndV" ," XorV" ," OrV" ,
4350+ " MaxV" , " MinV" , " MinVHF" , " MaxVHF" , " UMinV" , " UMaxV" ,
4351+ " CompressV" , " ExpandV" , " CompressM" , " CompressBitsV" , " ExpandBitsV" ,
4352+ " AddReductionVI" , " AddReductionVL" ,
4353+ " AddReductionVHF" , " AddReductionVF" , " AddReductionVD" ,
4354+ " MulReductionVI" , " MulReductionVL" ,
4355+ " MulReductionVHF" , " MulReductionVF" , " MulReductionVD" ,
4356+ " MaxReductionV" , " MinReductionV" ,
4357+ " AndReductionV" , " OrReductionV" , " XorReductionV" ,
4358+ " MulAddVS2VI" , " MacroLogicV" ,
4359+ " LShiftCntV" ," RShiftCntV" ,
4360+ " LShiftVB" ," LShiftVS" ," LShiftVI" ," LShiftVL" ,
4361+ " RShiftVB" ," RShiftVS" ," RShiftVI" ," RShiftVL" ,
4362+ " URShiftVB" ," URShiftVS" ," URShiftVI" ," URShiftVL" ,
4363+ " Replicate" ," ReverseV" ," ReverseBytesV" ,
4364+ " RoundDoubleModeV" ," RotateLeftV" , " RotateRightV" , " LoadVector" ," StoreVector" ,
4365+ " LoadVectorGather" , " StoreVectorScatter" , " LoadVectorGatherMasked" , " StoreVectorScatterMasked" ,
4366+ " SelectFromTwoVector" , " VectorTest" , " VectorLoadMask" , " VectorStoreMask" , " VectorBlend" , " VectorInsert" ,
4367+ " VectorRearrange" , " VectorLoadShuffle" , " VectorLoadConst" ,
4368+ " VectorCastB2X" , " VectorCastS2X" , " VectorCastI2X" ,
4369+ " VectorCastL2X" , " VectorCastF2X" , " VectorCastD2X" , " VectorCastF2HF" , " VectorCastHF2F" ,
4370+ " VectorUCastB2X" , " VectorUCastS2X" , " VectorUCastI2X" ,
4371+ " VectorMaskWrapper" ," VectorMaskCmp" ," VectorReinterpret" ," LoadVectorMasked" ," StoreVectorMasked" ,
4372+ " FmaVD" , " FmaVF" , " FmaVHF" , " PopCountVI" , " PopCountVL" , " PopulateIndex" , " VectorLongToMask" ,
4373+ " CountLeadingZerosV" , " CountTrailingZerosV" , " SignumVF" , " SignumVD" , " SaturatingAddV" , " SaturatingSubV" ,
4374+ // Next are vector mask ops.
4375+ " MaskAll" , " AndVMask" , " OrVMask" , " XorVMask" , " VectorMaskCast" ,
4376+ " RoundVF" , " RoundVD" ,
4377+ // Next are not supported currently.
4378+ " PackB" ," PackS" ," PackI" ," PackL" ," PackF" ," PackD" ," Pack2L" ," Pack2D" ,
4379+ " ExtractB" ," ExtractUB" ," ExtractC" ," ExtractS" ," ExtractI" ," ExtractL" ," ExtractF" ," ExtractD"
4380+ };
4381+ int cnt = sizeof (vector_list)/sizeof (char *);
4382+ if (_rChild) {
4383+ const char *opType = _rChild->_opType ;
4384+ for (int i=0 ; i<cnt; i++)
4385+ if (strcmp (opType,vector_list[i]) == 0 )
4386+ return true ;
4387+ }
4388+ return false ;
4389+ }
4390+
4391+
42844392bool MatchRule::skip_antidep_check () const {
42854393 // Some loads operate on what is effectively immutable memory so we
42864394 // should skip the anti dep computations. For some of these nodes
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