GitHub - Madhu-Krishnan-A-P/adder_subtractor: Verilog implementation of a 4-bit adder/subtractor using combinational logic with testbench and simulation output.

Name		Name	Last commit message	Last commit date
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4 bit adder subtractor.pdf		4 bit adder subtractor.pdf
addersub.sv		addersub.sv
testbench.sv		testbench.sv

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Verilog implementation of a 4-bit adder/subtractor using combinational logic with testbench and simulation output.

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