Improve single-qubit gate count in TwoQubitControlledUDecomposer

[ShellyGarion]

close #16036

This PR reduces the total number of 1-qubit unitaries needed to synthesize a general 2-qubit unitary using TwoQubitControlledUDecomposer from 24 to 8.

This is in particular useful for the peephole optimization in #13419.

Details:

The TwoQubitControlledUDecomposer consists of the following steps.

1. We start from a general 4x4 unitary U.

2. Then we find a cannonical gate W (Weyl gate) s.t.
   U(0,1) = c2r(0) c2l(1) W(0,1) c1r(0) c1l(1)
   this yields 4 1-qubit unitary gates.

     ┌─────┐┌───────┐┌─────┐
q_0: ┤ c2r ├┤0      ├┤ c1r ├
     ├─────┤│  Weyl │├─────┤
q_1: ┤ c2l ├┤1      ├┤ c1l ├
     └─────┘└───────┘└─────┘

3. Then, we write the Weyl gate W as:
   W(0,1) = RXX(0,1) RYY(0,1) RZZ(0,1)

     ┌─────────┐┌─────────┐        
q_0: ┤0        ├┤0        ├─■──────
     │  Rxx(a) ││  Ryy(b) │ │ZZ(c) 
q_1: ┤1        ├┤1        ├─■──────
     └─────────┘└─────────┘        

4. Now, we rewrite RYY(0,1) and RZZ(0,1) as:
   RYY(0,1) = sdg(0) sdg(0,1) RXX(0,1) s(0,1) s(0,1)
RZZ(0,1) = h(0) h(0,1) h(0,1) h(0,1) h(0,1)
   yielding 8 additional 1-qubit unitary gates.

     ┌─────┐┌─────────┐┌───┐
q_0: ┤ Sdg ├┤0        ├┤ S ├
     ├─────┤│  Rxx(b) │├───┤
q_1: ┤ Sdg ├┤1        ├┤ S ├
     └─────┘└─────────┘└───┘
     ┌───┐┌─────────┐┌───┐
q_0: ┤ H ├┤0        ├┤ H ├
     ├───┤│  Rxx(c) │├───┤
q_1: ┤ H ├┤1        ├┤ H ├
     └───┘└─────────┘└───┘

5. If Equiv is the target controlled-U gate (which is locally equivalent to RXX), then we rewrite RXX using Equiv:
   RXX(0,1) = k2r(0) k2l(1) Equiv(0,1) k1r(0) k1l(1)
   yielding 3*4 1-qubit unitary gates.

     ┌─────┐┌────────┐┌─────┐
q_0: ┤ k2r ├┤0       ├┤ k1r ├
     ├─────┤│  Equiv │├─────┤
q_1: ┤ k2l ├┤1       ├┤ k1l ├
     └─────┘└────────┘└─────┘

This gives a total of:
3*4 + 8 + 4 = 24 1-qubit unitary gates.

     ┌─────┐┌─────────┐┌───────────┐┌─────────┐┌─────┐┌─────────┐┌───────────┐»
q_0: ┤ c2r ├┤ rxx_k2r ├┤0          ├┤ rxx_k1r ├┤ Sdg ├┤ ryy_k2r ├┤0          ├»
     ├─────┤├─────────┤│  Equiv(a) │├─────────┤├─────┤├─────────┤│  Equiv(b) │»
q_1: ┤ c2l ├┤ rxx_k2l ├┤1          ├┤ rxx_k1l ├┤ Sdg ├┤ ryy_k2l ├┤1          ├»
     └─────┘└─────────┘└───────────┘└─────────┘└─────┘└─────────┘└───────────┘»
«     ┌─────────┐┌───┐┌───┐┌─────────┐┌───────────┐┌─────────┐┌───┐┌─────┐
«q_0: ┤ ryy_k1r ├┤ S ├┤ H ├┤ rzz_k2r ├┤0          ├┤ rzz_k1r ├┤ H ├┤ c1r ├
«     ├─────────┤├───┤├───┤├─────────┤│  Equiv(c) │├─────────┤├───┤├─────┤
«q_1: ┤ ryy_k1l ├┤ S ├┤ H ├┤ rzz_k2l ├┤1          ├┤ rzz_k1l ├┤ H ├┤ c1l ├
«     └─────────┘└───┘└───┘└─────────┘└───────────┘└─────────┘└───┘└─────┘

In this PR we multiply the 1-qubit unitary matrices betwen the 2-qubit gates, to get at most 8 1-qubit unitary gates (in the general case where 3 2-qubit gates are needed).

AI/LLM disclosure

• I didn't use LLM tooling, or only used it privately.
• I used the following tool to help write this PR description:
• I used the following tool to generate or modify code:

[coveralls]

Coverage Report for CI Build 25690415793

Warning

Build has drifted: This PR's base is out of sync with its target branch, so coverage data may include unrelated changes.
Quick fix: rebase this PR. Learn more →

Coverage increased (+0.05%) to 87.621%

Details

• Coverage increased (+0.05%) from the base build.
• Patch coverage: 6 uncovered changes across 1 file (190 of 196 lines covered, 96.94%).
• 764 coverage regressions across 18 files.

Uncovered Changes

File	Changed	Covered	%
crates/synthesis/src/two_qubit_decompose/controlled_u_decomposer.rs	196	190	96.94%

Coverage Regressions

764 previously-covered lines in 18 files lost coverage.

Top 10 Files by Coverage Loss	Lines Losing Coverage	Coverage
crates/circuit/src/dag_circuit.rs	398	84.69%
crates/circuit/src/circuit_drawer.rs	73	95.26%
qiskit/circuit/quantumcircuit.py	71	94.46%
crates/circuit/src/circuit_data.rs	52	87.17%
crates/circuit/src/parameter/parameter_expression.rs	51	91.04%
crates/circuit/src/register_data.rs	42	69.74%
crates/transpiler/src/passes/basis_translator/compose_transforms.rs	16	84.67%
crates/transpiler/src/commutation_checker.rs	14	88.79%
crates/transpiler/src/passes/commutation_cancellation.rs	10	91.38%
crates/circuit/src/interner.rs	9	97.02%

---

Coverage Stats

Relevant Lines:	122141
Covered Lines:	107021
Line Coverage:	87.62%
Coverage Strength:	963275.63 hits per line

---

💛 - Coveralls

[qiskit-bot]

One or more of the following people are relevant to this code:

• @Qiskit/terra-core
• @levbishop

[mtreinish]

Overall this looks good, thanks for fixing this. I just had a few comments inline.

[mtreinish]

Thanks for the updates, I just had a few more small comments inline.

[mtreinish]

Overall this LGTM now and is basically ready to merge. Thanks for doing this. I did pushed up a small couple of commits to cleanup some of the code (using a struct instead of a tuple so we get named access on the return from to_rxx_gate() and also renaming a couple of variables. I won't automerge it so you can review that you're ok with my changes before we merge. If you're ok with them feel free to enqueue for merging.

I also had a comment on the tests which we would be good to fix now, but also it isn't critical since it's really more a test of the euler one qubit decomposer.

[mtreinish]

I think we can tighten this up by adding a condition on the basis. Like right now none of the tests really check the 1q gate count for the U3, U321, or RR basis. We should maybe validate the gate count for a given basis matches the specified euler basis or make the check more generic and say we expect < n single qubit gates where n is determined by the euler basis.

[ShellyGarion]

Thanks for the fixes you've pushed - the code looks nicer now!

Since this test is quite complicated as it includes many combinations of 2-qubit gates and euler bases, this is just a sanity check (since we already have seperate tests for the euler decomposers).

The main check is that the maximal number of u gates is 8.
Similarly for ry gates as they appear only in ZYZ.
rx gates can appear only in ZXZ (at most 8 times), or XYX / XZX, so their number is at most 16.
The rz gate count is not tight (it's at most 8 in XZX, 16 at ZYZ and ZXZ and more in ZSX and ZSXX), but since they don't have an error, I don't care much about their counts for now.