Robs RISC-V

This is my CPU implementation of the RISC-V 32I base integar instruction set. It is implemented in SystemVerilog and verified with pyuvm, and cocotb-coverage, with a custom assembler writen in python.

I created it to learn the fundamentals about RISC-V and imporve my verification skill. I only spend about 2 weeks from start to finsh on the project, so if you're looking for a 100% reliable core this may not be the one for you.

Setup

cd verif
python3 -m venv .venv
source .venv/bin/activate
pip install pyuvm cocotb-coverage

Test everything

./run_all_tests.sh

Output	Path
Logs	verif/sim_build/<module_name>/pyuvm.log
Coverage	verif/sim_build/<module_name>/coverage.yaml
Waves	verif/sim_build/<module_name>/testbench_<module_name>.fst
Results	verif/sim_build/<module_name>/results.xml

Test a specific module

make DUT=<module_name> e.g.

make DUT=program_counter

Test the top with a specific assembly program

make top ASM_PROGRAM=<path_to_asm_file> e.g.

make top ASM_PROGRAM=top_pkg/programs/fibonacci.s

View waves

Wave files are saved to verif/sim_build/<module_name>/testbench_<module_name>.fst.

With GTKWave installed run make wave DUT=<module_name

make wave DUT=program_counter