TinyML_SOC v0.1.0

TinyML_SOC v0.1.0

首个公开版本，目标板为 Sipeed Tang Primer 25K (GW5A-25A)。

Highlights

• VexRiscv RV32IM SoC with TinyML_NPU submodule integration.
• QSPI XIP firmware/model layout: FPGA image at external Flash 0x000000, KWS image at 0x400000.
• Real-time KWS demo using the Tang Primer 25K I2S microphone, FreeRTOS firmware, UART structured logs, and 8 LED class output.
• Chinese-first documentation for architecture, memory map, flash layout, GW5A bring-up, verification, performance, limitations, and troubleshooting.

Validation

• make check: PASS.
• make soc-rtl gw5a-fw: PASS, firmware image 188608 bytes, Flash offset 0x00400000.
• make gw5a-bitstream: PASS, clock Fmax 55.157 MHz against the 50 MHz constraint; no port-unconnected warning pattern was found in the Gowin reports.
• make sim-vcs-testvector: PASS.
• make sim-vcs-pcm: PASS.
• make gw5a-demo-check: PASS on Tang Primer 25K with one, up, and down detected through FT2232 UART.

Notes

• No bitstream, ELF, firmware binary, waveform, training data, or local build output is included in this release.
• TinyML_NPU, VexRiscv, and FreeRTOS-Kernel are consumed as submodules.
• v0.1.0 supports only the current Tang Primer 25K / GW5A-25A 50 MHz real-time KWS path.