GitHub - kymmt80/MIPS_Pipeline: An Implementation of MIPS processor with pipeline architecture.

Name		Name	Last commit message	Last commit date
Latest commit History 2 Commits
ALU.v		ALU.v
ALU_controller.v		ALU_controller.v
ControlHazard.v		ControlHazard.v
EX_MEM.v		EX_MEM.v
ForwardingUnit.v		ForwardingUnit.v
HazardUnit.v		HazardUnit.v
ID_EX.v		ID_EX.v
IF_ID.v		IF_ID.v
MEM_WB.v		MEM_WB.v
adder.v		adder.v
controller.v		controller.v
data_mem.v		data_mem.v
datapath.v		datapath.v
inst_mem.v		inst_mem.v
mux2nton.v		mux2nton.v
mux3nton.v		mux3nton.v
processor.v		processor.v
register.v		register.v
register_file.v		register_file.v
testbench.v		testbench.v