A C++ pipeline based simulator of RSIC architecture.

Implemented a RISC 5-stage pipeline in C++ and ran a benchmark program to observe a 60% reduction in total execution time between the pipelined and unpipelined design.

Superscalar pipeline simulator features out-of-order execution, MSHR-based cache, and cycle-accurate power modeling.

5-stage in-order pipeline simulator in C: IF/ID/EX/MEM/WB stages, custom 11-opcode ISA, load-use stall detection, EX/MEM and MEM/WB data forwarding, 2-cycle branch/jump flush. Direct-mapped icache and dcache (64 lines, 4-cycle miss). Outputs cycle-by-cycle latch state, timing diagrams, CPI and cache stats.

Simulation of a 5-stage Pipeline in 5x Arduino UNO

C++17 computer architecture simulator with clean-sheet RISC ISA, assembler, 5-stage pipeline, L1/L2 cache hierarchy, CLI/Qt GUI, and benchmark cycle analysis.

Computer architecture simulators for in-order and out-of-order pipelines, configurable cache hierarchies, and dynamic branch prediction