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VaishnavaDevi-R / Memory-Management-Unit-Design-Using-Verilog-HDL

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Parameterizable 32-bit Memory Management Unit (MMU) designed in Verilog HDL featuring virtual memory translation, TLB-based address lookup, ASID-aware translation, Page Table Walker (PTW), permission checking, page and execute fault handling, self-checking verification testbenches & comprehensive waveform verification using Icarus Verilog & GTKwave

fpga riscv verilog memory-management virtual-memory computer-architecture mmu gtkwave vlsi verilog-hdl tlb iverilog semiconductor digital-design ptw cpu-design asic-design rtl-design hardware-design page-table
  • Updated Jun 20, 2026
  • Verilog

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