Caravel is a standard SoC template with on chip resources to control and read/write operations from a user-dedicated space.

Example designs showing different ways to use F4PGA toolchains.

VexRiscV system with GDB-Server in Hardware

A toy L4 load balancer running on FPGA

Briey SoC on ECP5 (ICESugar Pro)

Briey SoC on Sipeed Tang Primer

Yet another faux-retro game system

Co-architect 32-bit open-source RISC-V soft-cores for improved FPGA implementations

A small framework to simplify the creation of custom instruction for the VexRiscv.

TinyML_SOC is a GW5A-25 real-time keyword-spotting SoC integrating a VexRiscv CPU, TinyML_NPU, QSPI XIP firmware, an I2S microphone, UART logs, and LED results.

Source files and notes of my Final Year Project, as part of an MEng in Electronics and Information Engineering from Imperial College London

交大電子碩 系統晶片設計

交大電子碩 系統晶片設計 期末專題 第七組