AHB-Lite Slave Interface (Verilog HDL)

Overview

This project implements a simple AMBA AHB-Lite Slave Interface using Verilog HDL. It supports basic read and write transactions using four 32-bit registers. The project was designed as part of my learning in RTL design and AMBA AHB-Lite protocol.

Features

• Supports Read and Write Operations
• Four 32-bit Registers
• AHB-Lite Compatible Interface
• Verilog RTL Design
• Testbench Included
• Simulation Verified
• Waveform Analysis

Tools Used

• Verilog HDL
• Visual Studio Code
• Icarus Verilog
• GTKWave
• Git & GitHub

Repository Contents

• AHB_Lite_Slave.v – RTL design
• AHB_Lite_Slave_tb.v – Testbench
• Simulation output
• Waveform image (.png)
• Practice Verilog modules:
  • 2:1 Multiplexer
  • D Flip-Flop with Reset
  • 4-bit Counter
  • 4-bit Register

Simulation

The design was simulated using Icarus Verilog, and the waveform was analyzed using GTKWave. The simulation verifies correct read and write operations of the AHB-Lite Slave Interface.

Learning Outcomes

Through this project, I gained practical experience in:

• RTL Design using Verilog HDL
• Testbench Development
• Digital Circuit Simulation
• AMBA AHB-Lite Protocol Basics
• Git & GitHub Version Control

Future Improvements

• Support for Burst Transfers
• Wait State Handling
• Error Response Implementation
• Memory Interface Integration

Author

Sahithi Yadav
B.Tech in Electronics and Communication Engineering (ECE)
National Institute of Technology Srinagar