VeeR EH1 core

VeeR EL2 Core

Quasar 2.0: Chisel equivalent of SweRV-EL2

A Direct Memory Access Controller (DMAC) with AHB-lite bus interface

AHB-Lite Quad I/O SPI Flash memory controller with direct mapped cache and support for XiP

This Repo contains SystemC for testBench for AMBA® 3 AHB-Lite Protocol

Verilog AHB Bus implementation for VAAMAN

Arm Cortex-M0 DesignStart SoC on Spartan-6 (Atlys): VHDL AHB-Lite peripherals, bare-metal firmware, verified testbenches, CI.

Verilog implementation of an AMBA AHB-Lite Slave Interface with RTL design, testbench, simulation and waveform analysis.

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